1. Field of the Invention
The invention relates in general to a NOR architecture memory and an operation method thereof, and more particularly to a NOR architecture memory capable of reducing a delay of a word line and an operation method thereof.
2. Description of the Related Art
Non-volatile memories are used in various present applications, and a flash memory is one of the non-volatile memories. Data may be written into or read from the flash memory, and the data stored in the flash memory can be held without consuming any power. So, the flash memory has been used in various applications of data storage. The flash memory includes many memory cells arranged in an array having m rows and n columns, wherein m and n are positive integers. Each memory cell is enabled by a corresponding word line. When the flash memory is being operated, the corresponding bit line and the corresponding word line are enabled according to the to-be-operated memory cell.
The architectures of the flash memories may be classified into a NOR architecture and an NAND architecture. The NOR architecture flash memory has the advantage of high-speed random reading, but has the disadvantage of low writing speed, while the NAND architecture flash memory has the opposite advantage and opposite disadvantage. One of the trends of manufacturing the flash memory is to utilize the NOR architecture to implement the NAND specification to make the manufactured flash memory have both of the advantages. However, in order to implement NAND specification using NOR architecture, the word line may have a relative large resistance.
This relative-large resistance increases the RC time constant of the word line so that the NOR architecture flash memory has a delay when selecting the word line. So, it is an important subject to shorten the delay of the word line to make the word line be quickly charged to the target voltage. FIG. 1A (Prior Art) is a schematic illustration showing an example of a conventional word line. As shown in FIG. 1A, a driver 101, a driver 102 and a metal wire 103 are utilized such that a word line WL is charged from two sides simultaneously and the delay of the word line can be shortened.
FIG. 1B (Prior Art) is a schematic illustration showing another example of the conventional word line. As shown in FIG. 1B, a metal bypass 104 is utilized, and a metallic contact 105 is formed every N memory cells on the word line WL so that the word line WL may be rapidly charged through the metal bypass 104 and the metallic contact 105 and the delay of the word line may be shortened, wherein N is a positive integer. However, the above-mentioned methods can effectively shorten the delay of the word line, but the area of the flash memory is enlarged, and the requirement cannot be satisfied.